Dot matrix type running display panel for use in electronic calculators or the like

ABSTRACT

An electronic calculator with a dot matrix display panel capable of displaying characters, symbols or other patterns is implemented with a central processor unit (CPU). More particularly, when the length of characters is in excess of the capacity of the display panel, those characters are shifted dot by dot on the display panel in the running fashion. Numbers are displayed digit by digit, preferably.

BACKGROUND OF THE INVENTION

This invention relates to a display device for use in electroniccalculators or the like, and more particularly to a display device whichachieves a unique display operation.

In the past, when it was desired to display data of a length more thanthe capacity of a display panel in an electronic calculator, the data tobe displayed needed to be split into two or more groups in advance. Inthis case data expressing the same thought had to be split into groupswhich were inevitably separate and the connections between two adjacentones of the data groups were indefinite and vague, leading to operatorerrors in recognizing the overall or combined contents being displayed.To overcome this problem, the same applicants of this application haveproposed a unique device which shifts the contents of a display paneldigit by digit at a given interval of time, as disclosed and illustratedin U.S. application Ser. No. 058,666, filed July 18, 1979, and entitledDISPLAY DEVICE FOR ELECTRONIC CALCULATORS OR THE LIKE.

It is therefore an object of the present invention to provide a displaydevice which uses a dot matrix type display panel for displayingnumbers, characters, symbols and similar patterns and shiftssuccessively the overall contents on the display panel when the lengthof data to be displayed exceeds the capacity of the display panel,wherein the shifting movement of the display takes place dot by dot in alateral direction.

It is another object of the present invention to provide a displaydevice wherein either a conventional display mode (in other words, astatic display mode) or a dot shift display mode is selectable with theformer displaying keyed information or the results of arithmeticoperations, for example, and the latter displaying instructionsindicating the sequence of arithmetic operations in a dot matrix formmainly for use in function calculators.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and forfurther objects and advantages thereof, reference is now made to thefollowing description taken in conjunction with the accompanyingdrawings, in which:

FIG. 1 is a plan view of an example of a programmable calculatorembodying a display device according to the present invention;

FIG. 2 is a schematic block diagram of a circuit arrangement of theillustrated calculator;

FIG. 3 is a schematic block diagram of display control circuitry DSC inthe illustrated calculator;

FIGS. 4A through 4D are logic diagrams of an example of a centralprocessor unit (CPU) in the illustrated calculator;

FIG. 5 is a composite diagram of the CPU in the illustrated calculator;

FIG. 6 is a schematic representation of a dot matrix display panel inthe illustrated calculator;

FIG. 7(a) is an explanation diagram of a display pattern on the dotmatrix display panel and FIG. 7(b) is a table for numerical binarycodes;

FIG. 8 is a block diagram of a displaying data storage area;

FIG. 9 is a block diagram of part of a random access memory (RAM) of theCPU architecture;

FIG. 10 is a flow chart for explanation of the display operation in theillustrated calculator;

FIGS. 11(a) through 11(c) are details of the operation shown in FIG. 10;

FIG. 12(a) shows the relationship between respective steps and a processlist and FIG. 12(b) is the relationship between the respective steps andapplied routines;

FIG. 13 is a table showing the relationship between characters and theirencoded signals;

FIG. 14 shows a program for storing encoded signals for displaying acharacter "I";

FIG. 15(a) is a program for shifting the contents of the displaying datastorage area and FIG. 15(b) shows events for achieving the shiftoperation; and

FIG. 16 is a flow chart of a display operation for keyed information.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 1, there is illustrated a plan view of aprogrammable calculator having a display device constructed inaccordance with one preferred form of the present invention, wherein adisplay device is generally designated DSP and a keyboard unit isgenerally designated K.

FIG. 2 shows in a block diagram the programmable calculator whichincludes a central processor unit CPU (hereinafter referred to as"CPU"), the display device DSP, for example, in the form of a liquidcrystal display panel of the dot matrix type, display control circuitryDSC for enabling the display device, a random access memory RAMcontained within the CPU and a displaying data storage area DRMcomprised of a random access memory (RAM) contained within the displaycontrol circuitry. It further includes key strobe output terminals W₁-W₈, key input terminals k₁ -k₄, opposing electrodes signal outputterminals H₁ -H₇, a memory digit address output terminal B_(L) T, amemory file address output terminal B_(M) T, a read/write signalterminal R/W, a display (disable) control signal output terminal DIS anddata input output terminals DI/O.

Details of the display control circuitry in FIG. 2 are illustrated in ablock diagram of FIG. 3. Within the display control circuitryillustrated herein, an address decoder DC₆ is connected to thedisplaying data storage area DRM, which decoder decodes signals from thememory digit address output terminal B_(L) and the memory file addressoutput terminal B_(M) via an address buffer AB. A read/write controlcircuit RWC receives a read/write signal from the R/W terminal andachieves read and write operations on the information in the displayingdata storage area via the data input output terminals DI/O. There arealso provided a displaying buffer DM and a segment driver SED fordecoding the area DM. When the display disable signal terminal is at "1"or "0", SED provides an ON or OFF waveform output, respectively. Segmentsignal output terminals are labeled S₁ -S₄₀. FIG. 4, a composite diagramof FIGS. 4A through 4D, shows a logic wiring diagram of the CPU schemein the calculator whereby the display operation of the present inventionis effected. FIG. 5 shows how to combine FIGS. 4A-4D concerning the CPU.The following will set forth a logic structure of the CPU.

[CPU ARCHITECTURE]

RAM (random access memory): this is of a 4 bit input and output capacityand accessible to a specific digit position thereof as identified by adigit address and a file address.

BL: a digit address counter associated with the memory RAM, with anoutput terminal B_(L) T.

DC₁ : a digit address decoder associated with the memory RAM.

BM: a file address counter associated with the memory RAM, will anoutput terminal B_(M) T.

DC₂ : a file address decoder for the memory RAM

AD₁ : this serves as an adder and a subtractor respectively in theabsence and presence of a control instruction 14 .

AD₂ : an adder

G₁ : a gate for providing either a digit "1" or an operand I_(A) to aninput to the adder/subtractor AD₁ and delivering I or I_(A) when acontrol instruction 15 or 16 is developed, respectively.

SB: a count down circuit for the memory digit address counter BL.

G₂ : an input gate provided for the memory digit address counter BL,which enables the output of the adder/subtractor AD₁, the operand I_(A),another operand I_(B) and the output of the count down circuit SB topass therethrough respectively when control instructions 10 , 11 , 12and 74 are developed.

G₃ : a gate provides a digit "1" or the operand I_(A) to an input to theadder/subtractor, the former being provided upon the developed of aninstruction 5 and the latter upon the development of an instruction 6 .

ED: an exclusive OR gate receiving the contents of the memory fileaddress counter BM and the accumulator ACC and providing its output fora gate G₄.

G₄ : an input gate to the memory file address BM which enables theoutput of the adder AD₂, the operand I_(A) the contents of anaccumulator ACC, and the output of EO to pass upon the development ofinstructions 7 , 8 , 9 and 85 .

G₅ : a file selection gate for the memory RAM

DC₃ : a decoder which translates the operand I_(A) and supplies a gateG₆ with a desired bit specifying signal.

G₆ : an input gate to the memory RAM, which contains a circuitarrangement for introducing a binary code "1" into a specific bitposition of the memory identified by the operand decoder DC₃ and abinary code "D" into a specific bit position identified by DC₃,respectively, when a control instruction 2 or 3 is developed. Upon thedevelopment of an instruction 11 4 the contents of the accumulator ACCare read out.

ROM: a read only memory

N₁, N₂ : display controlling flags

G₄₆ : an input gate to N₁ and N₂, which is turned ON upon 69.

RW: a read/write signal generator with its output terminal R/W, whcichexecutes read or write operation upon 70 or 71 , respectively.

PL: a program counter PL which specifies a desired step in the read onlymemory ROM.

DC₄ : a step access decoder for the read only memory ROM.

G₇ : an output gate which shuts off transmission of the output of theROM to an instruction decoder DC₅ when a judge flip flop F/F J is set.

DC₅ : an instruction decoder adapted to decode instruction codes derivedfrom the ROM and divide them into an operation code area I_(O) andoperand areas I_(A) and I_(B), the operation code being decoded into anycontrol instruction 1 - 75 . The decoder DC₅ is further adapted tooutput the operand I_(A) or I_(B) as it is when sensing an operationdoce accompanied by an operand.

AD₃ : an adder increments one the contents of the program counter PL.

G₈ : an input gate associated with the program counter PL provides theoperand I_(A) and transmits the contents of a program stack register SPwhen the instructions 20 and 61 are developed, respectively. When theinstructions 20 , 61 and 60 are being processed, any output of the adderAD₃ is not transmitted. Otherwise the AD₃ output is transmitted toautomatically load "1" into the contents of the program counter PL.

FC: a flag F/F

G₉ : an input gate for the flag F/F FC, which introduces binary codes"1" and "0" into the flag flip flop FC when the instructions 17 and 18are developed, respectively.

G₁₀ : a key signal generating gate provides the output of the memorydigit address decoder DC₁ without any change when the flag F/F FC is inthe reset state (0), and renders all outputs I₁ -I_(n) "1" whateveroutput DC₁ provides when FC is in the set state (1).

CG: a clock generator

BP: an opposing electrode signal generator for the liquid crystaldisplay panel

H₁ -H₇ : The opposing electrode signal output terminals

ACC: an accumulator of 4 bits long

X: a temporary register of 4 bits long

G₁₁ : an input gate for the temporary register X transmits the contentsof the accumulator ACC and the stack register SX respectively upon thedevelopment of the instructions 29 and 59 .

AD₄ : an adder executes a binary addition on the contents of theaccumulator ACC and other data. The output C₄ of the adder AD₄ assumes"1" when the fourth bit binary addition yields a carry.

C: a carry F/F

G₁₂ : an input gate for the carry F/F, which sets "1" into the carry F/FC in the presence of "1" of the fourth bit carry C₄ and "0" into thesame in the absence of C₄ (0) upon the development of 1 . "1" and "0"are set into C upon the development of 21 and 22 , respectively.

G₁₃ : a carry (C) input gate enables the adder AD₄ to perform binaryadditions with a carry and thus transmits the output of the carry F/F Cinto the adder AD₄ in response to the instruction 25 .

G₁₄ : an input gate provided for the adder AD₄ and transfers the outputof the memory RAM and the operand I_(A) upon the development of 23 and24 , respectively.

F: an output buffer register having a 4-bit capacity.

G₁₅ : an input gate which enables the contents of the accumulator ACC toenter into F upon the development of 31 .

SD: an output decoder decodes the contents of the output buffer F intodisplay segment signals SS₁ -SS_(n).

W: an output buffer register

SHC: a shift circuit for the output buffer register, which shifts theoverall bit contents of the output buffer register W one bit to theright at a time in response to 32 or 33 .

G₁₆ : an input gate for the output buffer register W leads "1" and "0"into the first bit position of W upon 32 and 33 , respectively.Immediately before "1" or "0" enters into the first bit position of Wthe output buffer shift circuit SHC becomes operative.

NP: an output control flag F/F.

G₁₇ : an input gate to the output control flag F/F for receiving "1" and"0" upon the development of 34 and 35 , respectively.

G₁₈ : an output control gate provided for the buffer register W forproviding the respective bit outputs thereof at one time only when theflag F/F NP is in the set state (1). The output signals of the Wregister are used as the key strobe signals.

J: a judge F/F

IV₁ -IV₄ : inverter circuits

G₁₉ : an input gate for the judge F/F J for transferring the state of aninput KN₁ into J upon the development of 36 . In the case where KN₁ =0,J=1 because of intervention of the inverter IV₁.

G₂₀ : an input gate for the judge F/F J adapted to transfer the state ofan input KN₂ into J upon 37 . When KN₂ =0, J=1 because of interventionof the inverter IV₂.

G₂₁ : an input gate for the judge F/F J adapted to transfer the state ofan input KF₁ into J upon 38 . When KF₁ =0, J=1 because of the inverterIV₃.

G₂₂ : an input gate for the judge F/F J adapted to transfer the state ofthe input KF₂ into J upon 39 . When KF₂ =0, J=1 because of theintervening inverter IV₄.

G₂₃ : an input gate provided for the judge flip flop J for transmissionof the state of an input AK into J upon the development of 40 . WhenAK=1, J=1.

G₂₄ : an input gate G₂₄ is provided for the judge flip flop J totransmit the state of an input TAB into J pursuant to 41 . When TAB=1,J=1.

G₂₅ : a gate provided for setting the judge F/F J upon the developmentof 46 .

V₁ : a comparator compares the contents of the memory digit addresscounter BL with preselected data and provides an output "1" if there isagreement. The comparator V₁ becomes operative when 43 or 44 isdeveloped.

G₂₆ : an input gate to the comparator V₁. The data n₁ to be compared isa specific higher address value which is often available in controllingthe RAM. n₁ and n₂ are provided for comparison purposes upon thedevelopment of 43 and 44 , respectively.

G₂₇ : an input gate provided for the decision F/F J to enter "1" into Jwhen the carry F/F C assumes "1" upon the development of 45 .

DC₆ : a decoder decodes the operand I_(A) and helps decisions as towhether or not the contents of a desired bit position of the RAM are"1".

G₂₈ : a gate transfers the contents of the RAM as specified by theoperand decoder DC₆ into the judge F/F when 46 is derived. When thespecified bit position of the RAM assumes "1", J=1.

V₂ : a comparator decides whether or not the contents of the accumulatorACC are equal to the operand I_(A) and provides an output "1" when theaffirmative answer is provided. The comparator V₂ becomes operativeaccording to 47 .

V₃ : a comparator decides under 48 whether the contents of the memorydigit address counter BL are equal to the operand I_(A) and provides anoutput "1" when the affirmative answer is obtained.

V₄ : a comparator decides whether the contents of the accumulator ACCagree with the contents of the RAM and provides an output "1" in thepresence of the agreement.

G₂₉ : a gate which transfers the fourth bit carry C₄ occurring duringaddition into the judge F/F J. Upon the development of 50 C₄ is sent toF/F J. J=1 in the presence of C₄.

F_(A) : a flag F/F

G₃₁ : an input gate to the flag F/F FA which provides outputs "1" and"0" upon the development of 52 and 53 , respectively.

G₃₂ : an input gate provided for setting the judge F/F J when the flagflip flop FA assumes "1".

F_(B) : a flag F/F

G₃₃ : an input gate for the flag F/F, which provides outputs "1" and "0"upon 55 and 56 , respectively.

G₃₄ : an input gate for the judge flip flop J is adapted to transfer thecontents of the flag flip flop F_(B) into the F/F J upon the developmentof 52 .

G₄₄ : an input gate to the judge F/F J to transfer the contents of theinput under control of 68 . J=1 when α=1.

G₃₅ : an input gate associated with the judge F/F J is provided fortransmission of the contents of an input β upon 19 . When β=1, J=1.

G₄₅ : a gate to transfer the contents of the accumulator ACC into theinput output terminal D_(1/O) of the displaying data storage area DRMupon receipt of 73 .

G₃₆ : an input gate associated with the accumulator ACC is provided fortransferring the output of the adder AD₄ upon 26 and transferring thecontents of the accumulator ACC after being inverted by an inverter IV₅upon 27 . The contents of the memory RAM are transferred upon 28 , theoperand I_(A) upon 13 , the 4 bit input contents k₁ -k₄ upon 57 , andthe contents of the stack register SA upon 59 . The data from thestorage area DRM are fed via D_(I/O) upon 72 .

IV₅ : an inverter circuit

SA: a stack register provides the output outside the present system.

SX: a stack register which also provides the output outside the system.

G₃₇ : an input gate associated with the stack register SA transfers theaccumulator ACC upon 58 .

G₃₈ : an input gate associated with the stack register SX transfers thecontents of the temporary register X upon 58 .

SP: a program stack register

G₃₉ : an input gate associated with the program stack register forloading the contents of the program counter PL incremented by "1"through the adder into the program stack register upon 60 .

An illustrative example of the instruction codes contained within theROM of the CPU structure, the name and function of the instruction codesand the control instructions developed pursuant to the instruction codeswill now be tabulated in Table 1 wherein the following correspondencesexist A: the instruction codes, B: the instruction name, C: theinstruction description and D: the CPU control instructions.

                                      TABLE 1                                     __________________________________________________________________________    A         B      D                                                            __________________________________________________________________________    1 I.sub.O SKIP ○42                                                     2 I.sub.O AD   ○23 ,○26                                         3 I.sub.O ADC  ○23 ,○26 ,○25 ,○1                  4 I.sub.O ADCSK                                                                              ○23 ,○26 ,○25 ,○50 ,○1                     1                                                              5 I.sub.O                                                                           I.sub.A                                                                           ADI  ○24 ,○26 ,○50                             6 I.sub.O                                                                           I.sub.A                                                                           DC   ○24 ,○26 ,○50                             7 I.sub.O SC   ○21                                                     8 I.sub.O RC   ○22                                                     9 I.sub.O                                                                           I.sub.A                                                                           SM   ○2                                                      10                                                                              I.sub.O                                                                           I.sub.A                                                                           RM   ○3                                                      11                                                                              I.sub.O COMA ○27                                                     12                                                                              I.sub.O                                                                           I.sub.A                                                                           LDI  ○13                                                     13                                                                              I.sub.O                                                                           I.sub.A                                                                           L    ○28 ,○8                                          14                                                                              I.sub.O                                                                           I.sub.A                                                                           LI   ○28 ,○8 ,○15 ,○10 ,○43                     4                                                              15                                                                              I.sub.O                                                                           I.sub.A                                                                           XD   ○28 ,○8 ,○14 ,○15 ,○10                     ,○ 44                                                   16                                                                              I.sub.O                                                                           I.sub.A                                                                           X    ○28 ,○4 ,○8                               17                                                                              I.sub.O                                                                           I.sub.A                                                                           XI   ○28 ,○4 ,○8 ,○15 ,○10                      ,○43                                                    18                                                                              I.sub.O                                                                           I.sub.A                                                                           XD   ○28 ,○4 ,○8 ,○14 ,○15                      ,○10 ,○44                                        19                                                                              I.sub.O                                                                           I.sub.A                                                                           LBLI ○11                                                     20                                                                              I.sub.O                                                                          I.sub.A                                                                         I.sub.B                                                                          LB   ○8 ,○12                                          21                                                                              I.sub.O                                                                           I.sub.A                                                                           ABLI ○16 ,○10 ,○43                             22                                                                              I.sub.O                                                                           I.sub.A                                                                           ABMI ○6 ,○7                                           23                                                                              I.sub.O                                                                           I.sub.A                                                                           T    ○20                                                     24                                                                              I.sub.O SKC  ○45                                                     25                                                                              I.sub.O                                                                           I.sub.A                                                                           SKM  ○46                                                     26                                                                              I.sub.O                                                                           I.sub.A                                                                           SKBI ○48                                                     27                                                                              I.sub.O                                                                           I.sub.A                                                                           SKAI ○47                                                     28                                                                              I.sub.O SKAM ○49                                                     29                                                                              I.sub.O SKN.sub.1                                                                          ○36                                                     30                                                                              I.sub.O SKN.sub.2                                                                          ○37                                                     31                                                                              I.sub.O SKF.sub.1                                                                          ○38                                                     32                                                                              I.sub.O SKF.sub.2                                                                          ○39                                                     33                                                                              I.sub.O SKAK ○40                                                     34                                                                              I.sub.O SKTAB                                                                              ○41                                                     35                                                                              I.sub.O SKFA ○51                                                     36                                                                              I.sub.O SKEB ○54                                                     37                                                                              I.sub.O WIS  ○32                                                     38                                                                              I.sub.O WIR  ○33                                                     39                                                                              I.sub.O NPS  ○34                                                     40                                                                              I.sub.O NPR  ○35                                                     41                                                                              I.sub.O ATF  ○31                                                     42                                                                              I.sub.O LXA  ○29                                                     43                                                                              I.sub.O XAX  ○29 ,○30                                         44                                                                              I.sub.O SFA  ○52                                                     45                                                                              I.sub.O RFA  ○53                                                     46                                                                              I.sub.O SFB  ○55                                                     47                                                                              I.sub.O RFB  ○56                                                     48                                                                              I.sub.O SFC  ○17                                                     49                                                                              I.sub.O RFC  ○18                                                     50                                                                              I.sub.O SFD  ○62                                                     51                                                                              I.sub.O RFD  ○63                                                     52                                                                              I.sub.O SFE  ○65                                                     53                                                                              I.sub.O RFE  ○66                                                     54                                                                              I.sub.O SKA  ○68                                                     55                                                                              I.sub.O SKB  ○19                                                     56                                                                              I.sub.O KTA  ○57                                                     57                                                                              I.sub.O STPO ○58                                                     58                                                                              I.sub.O EXPO ○58 ,○59                                         59                                                                              I.sub.O                                                                           I.sub. A                                                                          TML  ○62 ,○20                                         60                                                                              I.sub.O RIT  ○61                                                     61                                                                              I.sub.O                                                                          I.sub.A                                                                         I.sub.B                                                                          LNI  ○69                                                     62                                                                              I.sub.O READ ○70 ,○72                                         63                                                                              I.sub.O STOR ○71 ,○73                                         64                                                                              I.sub.O                                                                           I.sub.A                                                                           EX   ○28 ,○4 ,○75 ,○16                  65                                                                              I.sub.O DECB ○74 ,                                                   __________________________________________________________________________

Instruction Description (C) (1) SKIP

Only the program counter PL is incremented without executing a nextprogram step instruction, thus skipping a program step.

(2) AD

A binary addition is effected on the contents of the accumulator ACC andthe contents of the RAM, the addition results being loaded back into theaccumulator ACC.

(3) ADC

A binary addition is effected on the contents of the accumulator ACC,the memory RAM and the carry F/F C, the results being loaded back to theaccumulator ACC.

(4) ADCSK

A binary addition is effected on the contents of the accumulator ACC,the memory RAM and the carry flip flop C, the results being loaded intothe accumulator ACC. If the fourth bit carry C₄ occurs in the results,then a next program step is skipped.

(5) ADI

A binary addition is effected upon the contents of the accumulator ACCand the operand I_(A) and the results are loaded into the accumulatorACC. If the fourth bit carry C₄ is developed in the addition results,then a next program step is skipped.

(6) DC

The operand I_(A) is fixed as "1010" (a decimal number "10") and abinary addition is effected on the contents of the accumulator ACC andthe operand I_(A) in the same way as in the ADI instruction. The decimalnumber 10 is added to the contents of the accumulator ACC, the resultsof the addition being loaded into ACC.

(7) SC

The carry F/F C is set ("1" enters into C).

(8) RC

The carry F/F C is reset ("0" enters into C).

(9) SM

The contents of the operand I_(A) are decoded to give access to adesired bit position of the memroy specified by the operand ("1"enters).

(10) RM

The contents of the operand I_(A) are interpreted to reset a desired bitposition of the memory specified by the operand ("0" enters).

(11) COMA

The respective bits of the accumulator ACC are inverted and theresulting complement to "15" is introduced into ACC.

(12) LDI

The operand I_(A) enters into the accumulator ACC.

(13) L

The contents of the memory RAM are sent to the accumulator ACC and theoperand I_(A) to the file address counter BM.

(14) LI

The contents of the memory RAM are sent to the accumulator ACC and theoperand I_(A) to the memory file address counter BM. At this time thememory digit address counter BL is incremented. If the contents of BLagree with the preselected value n₁, then a next program step isskipped.

(15) XD

The contents of the memory RAM are exchanged with the contents of ACCand the operand I_(A) is sent to the memory file address counter BM. Thememory digit address counter BL is decremented. In the event that thecontents of BL agree with the preselected value n₂, then a next programstep is skipped.

(16) X

The contents of the memory RAM are exchanged with the contents of theaccumulator ACC and the operand I_(A) is loaded into the memory fileaddress counter BM.

(17) XI

The contents of the memory RAM are exchanged with the contents of theaccumulator ACC and the operand I_(A) is sent to the memory file addresscounter BM. The memory digit address counter BL is incremented. In theevent that BL is equal to the preselected value n₁, a next program stepis skipped.

(18) XD

The contents of the memory RAM replaces the contents of the accumulatorACC, the operand I_(A) being sent to the memory file address counter BM.The memory digit address counter BL at this time is incremented. If thecontents of BL are equal to n₂, then a next program step is skipped.

(19) LBLI

The operand I_(A) is loaded into the memory digit address counter BL.

(20) LB

The operand I_(A) is loaded into the memory file address counter BM andthe operand B to the memory digit address counter BL.

(21) ABLI

The operand I_(A) is added to the contents of the memory digit addresscounter BL in a binary addition fashion, the results being loaded backto BL. If the contents of BL are equal to n₁, then no next program stepis carried out.

(22) ABMI

The operand I_(A) is added to the contents of the memory file addresscounter BM in a binary fashion, the results being loaded into BM.

(23) T

The operand I_(A) is loaded into the program step counter PL.

(24) SKC

If the carry flip flop C is "1", then no next program step is taken.

(25) SKM

The contents of the operand I_(A) are decoded and a next program step isskipped as long as a specific bit position of the memory specified bythe operand I_(A) assumes "1".

(26) SKBI

The contents of the memory digit address counter BL are compared withthe operand I_(A) and a next succeeding program step is skipped whenthere is agreement.

(27) SKAI

The contents of the accumulator ACC are compared with the operand I_(A)and if both are equal to each other a next program step is skipped.

(28) SKAM

The contents of the accumulator ACC are compared with the contents ofthe RAM and if both are equal a next program step is skipped.

(29) SKN₁

When the input KN₁ is "0", a next program step is skipped.

(30) SKN₂

When the input KN₂ is "0", a next program step is skipped.

(31) SKF₁

When the input KF₁ is "0", a next program step is skipped.

(32) SKF₂

When the input KF₂ is "0", a next program step is skipped.

(33) SKAK

When the input AK is "1", a next program step is skipped.

(34) SKTAB

When the input TAB is "1", a next program step is skipped.

(35) SKFA

When the flag flip flop F/A assumes "1" a next program step is skipped.

(36) SKFB

When the flag flip flop F_(B) assumes "1", a next program step isskipped.

(37) WIS

The contents of the output buffer register W are one bit right shifted,the first bit position (the most significant bit position) receiving"1".

(38) WIR

The contents of the output buffer register W are one bit right shifted,the first bit position (the most significant bit position being loadedwith "0".

(39) NPS

The output control F/F N_(p) for the buffer register W is set ("1"enters).

(40) NPR

The buffer register output control flip flop N_(p) is reset ("0" enterstherein).

(41) ATF

The contents of the accumulator ACC are transferred into the outputbuffer register F.

(42) LXA

The contents of the accumulator ACC are unloaded into the temporaryregister X.

(43) XAX

The contents of the accumulator ACC are exchanged with the contents ofthe temporary register X.

(44) SFA

The flag F/F FA is set (an input of "1").

(45) RFA

The flag F/F FA is reset (an input of "0").

(46) SFB

The flag flip flop F_(B) is set (an input of "1").

(47) RFB

The flag flip flop F_(B) is reset (an input of "0").

(48) SFC

An input testing flag F/F F_(C) is set (an input of "1").

(49) RFC

The input testing flag F/F F_(C) is reset (an input of "0").

(50) SFC

The input testing flag F/F F_(D) is set (an input of "1").

(51) RFD

The input testing flag F/F F_(D) is reset (an input of "0").

(52) SFE

The input testing flag F/F F_(E) is set (an input of "1").

(53) RFE

The input testing flag F/F F_(E) is set (an input of "1").

(54) SKA

When an input α is "1", a next program step is skipped.

(55) SKB

When an input β is "1", a next program step is skipped.

(56) KTA

The inputs k₁ -k₄ are introduced into the accumulator ACC.

(57) STPO

The contents of the accumulator ACC are sent to the stack register SAand the contents of the temporary register X to the stack register SX.

(58) EXPO

The contents of the accumulator ACC are exchanged with the stackregister SA and the contents of the temporary register X with the stackregister SX.

(59) TML

The contents of the program counter P_(L) incremented by one aretransferred into the program stack register SP and the operand I_(A)into the program counter P_(L).

(60) RIT

The contents of the program stack register SP are transmitted into theprogram counter P_(L).

Table 2 sets forth the relationship between the operation codescontained within the ROM of the CPU structure and the operand.

                  TABLE 4                                                         ______________________________________                                         ##STR1##                                                                      ##STR2##                                                                      ##STR3##                                                                      ##STR4##                                                                      ##STR5##                                                                     ______________________________________                                         wherein I.sub.O : the operation codes and I.sub.A, I.sub.B : the operands

Taking an example wherein the output of the read only memory ROM is 10bit long, the instructoin decoder DC₅ decides whether the instruction ADor COMA (see TAble 1) assumes "0001011000" or "0001011111" and developsthe control instructions 23 , 26 , or 27 . SKBI is identified by thefact that the upper six bits assume "000110", the lower 4 bits "0010"being treated as the operand I_(A) and the remaining ninth and tenthbits "11" as the operand I_(B). The operand forms part of instructionwords and specifies data and addresses for next succeeding instructionsand can be called an address area of an instruction.

Major processing operaitons (a processing list) of the CPU structurewill now be described in sufficient detail.

[PROCESSING LIST]

(I) A same numeral N is loaded into a specific region of the memory RAM(NNN→X)

(II) A predetermined number of different numerals are loaded into aspecific region of the memory (N₁, N₂, N₃, . . . →X)

(III) The contents of a specific region of the memory are transferredinto a different region of the memory (X→Y)

(IV) The contents of a specific region of the memory are exchanged withthat of a different region (X←→Y)

(V) A given numeral N is added or subtracted in a binary fashion fromthe contents of a specific region of the memory (X±N)

(VI) The contents of a specific region of the memory are added in adecimal fashion to the contents of a different region (X±Y)

(VII) The contents of a specific region of the memory are one digitshifted (X right, X left).

(VIII) A one bit conditional F/F associated with a specific region ofthe memory is set or reset (F set, F reset)

(IX) The state of the one bit conditional F/F associated with a specificregion of the memory is sensed and a next succeeding program address ischanged according to the results of the state detection.

(X) It is decided whether the digit contents of a specific region of thememory reach a preselected numeral and a next succeeding program step isaltered according to the results of such decision.

(XI) It is decided whether the plural digit contents of a specificregion of the memory are equal to a preselected numeral and a programstep is altered according to the results of the decision.

(XII) It is decided whether the digit contents of a specific region ofthe memory are smaller than a given value and a program step to be nextexecuted is changed according to the decision.

(XIII) It is decided whether the contents of a specific region of thememory are greater than a given value and the results of such decisionalter a program step to be next executed.

(XIV) The contents of a specific region of the memory are displayed.

(XV) What kind of a key switch is actuated is decided.

The above processing events in (1)-(15) above are executed according tothe instruction codes step by step in the following manner.

(I) PROCEDURE OF LOADING A SAME VALUE N INTO A SPECIFIC REGION OF THEMEMORY (NNN→X)

    ______________________________________                                        (Type 1)                                                                      ______________________________________                                         ##STR6##                                                                     ______________________________________                                    

P₁ . . . The first digit position of the memory to be processed isspecified by a file address m_(A) and a digit address n_(E).

P₂ . . . The value N is loaded into ACC.

P₃ . . . The value N is loaded into the specified region of the memoryby exchange between the memory and ACC. With no change in the fileaddress of the memory, m_(A) is specified and the digit address isdecremented to determine a digit to be next introduced. By determing n₂as the final digit value n_(A) to be introduced, the next step P₄ isskipped to complete the processing of the Type 1 since BL=n₂ under thecondition that the value N has been completely loaded into the specificregion.

P₄ . . . LDI and XD are carried out repeatedly from the program addressP₂ up to BL=V.

    ______________________________________                                        (Type 2)                                                                      ______________________________________                                         ##STR7##                                                                     ______________________________________                                    

P₁ . . . The digit of the memory to be processed is determined by thefile address m_(B) and the digit address n_(C).

P₂ . . . The ACC is loaded with the value N.

P₃ . . . By exchange between the memory and ACC the value N is loadedinto the above specified region of the memory. This completes theprocessing of Type 2. An operand area of X_(D) is necessary to the nextsucceeding proce-s and not to this step.

    ______________________________________                                        (Type 3)                                                                      ______________________________________                                         ##STR8##                                                                     ______________________________________                                    

P₁ . . . The first digit of the memory to be processed is specified bythe file address m_(C) and the digit address n_(O).

P₂ . . . The ACC is loaded with the value N.

P₃ . . . By exchange between the memory and ACC the value N is loadedinto that specified region of the memory. With no change in the fileaddress of the memory m_(C) is specified and the digit address isdecremented in order to determine the digit to be next loaded therein.

P₄ . . . It is decided whether the digit processed during the step P₃ isthe final digit n_(B). If it is n_(B), then the digit address isdecremented to n_(A). An operand area of the SKI instruction is occupiedby n_(A), thus loading the final digit with the value N. In reaching P₄,conditions are fulfilled and the next step P₅ is skipped, therebyterminating the type 3. If the conditions are not fulfilled, P₅ is thenreached.

P₅ . . . The program address P₂ is specified and P₂ -P₄ are repeateduntil BL=n_(A).

(II) PROCEDURE OF LOADING A PREDETERMINED NUMBER OF DIFFERENT VALUESINTO A SPECIFIC REGION OF THE MEMORY (N₁, N₂, N₃, . . . →X)

    ______________________________________                                        (Type 1) For example, for digit values N.sub.4 N.sub.3 N.sub.2 N.sub.1        are                                                                           loaded an arbitraray digit position in the same manner -as                    ______________________________________                                        above.                                                                         ##STR9##                                                                     ______________________________________                                    

P₁ . . . The first processed digit position of the memory is specifiedby the file address m_(A) and the digit address n_(E).

P₂ . . . A constant N₁ is loaded into ACC.

P₃ . . . Through exchange between the memory and the ACC the value N₁ isloaded into the above specified region of the memory. The file addressof the memory remains unchanged as m_(A), whereas the digit address isup for introduction of the next digit.

P₄ . . . A second constnat N₂ is loaded into ACC.

P₅ . . . Since the second digit of the memory has been specified duringP₃, the second constant N₂ is loaded into the second digit position ofthe memory through exchange between the memory and ACC.

P₆ -P₉ . . . The same as in the above paragraph.

    ______________________________________                                        (Type 2)                                                                      Any value of 0-15 is loaded into a predetermined register.                    ______________________________________                                         ##STR10##                                                                    ______________________________________                                    

P₁ . . . The value N is loaded into ACC.

P₂ . . . The value N is transmitted from ACC into the register X.

(III) PROCEDURE OF TRANSFERRING THE CONTENTS OF A SPECIFIC REGION OF THEMEMORY TO A DIFFERENT REGION OF THE MEMORY (X→Y)

    ______________________________________                                        (Type 1)                                                                      ______________________________________                                         ##STR11##                                                                    ______________________________________                                    

P₁ . . . The first memory file address is specified as m_(A) and thefirst digit address as n_(E).

P₂ . . . The contents of the first digit position of the memory areloaded into ACC and its designation, the second memory file address isspecified as m_(B) prior to the transmission step P₃.

P₃ . . . The first digit memory contents loaded into the ACC arereplaced by the same second memory digit contents so that the firstmemory contents are transmitted into the second memory. In order torepeat the above process, the first memory file address m_(A) is againset. The value of the final digit n_(A) to be transmitted is previouslyselected to be n₁. Since BL→n₁ after the overall first memory contentshave been sent to the second memory, the next step P₄ is skipped tocomplete the processing of Type 1. The digit address is progressivelyincremented until BL=V (the final digit). Through the step P₄ the fileaddress is set up at m_(A) to lead back to P₂, thereby specifying thefirst memory.

P₄ . . . The program address is set at the step P₂ and the instructionsP₂ and P₃ are repeatedly executed until BL=n₁. The transmission step isadvanced digit by digit.

    ______________________________________                                        (Type 2)                                                                      ______________________________________                                         ##STR12##                                                                    ______________________________________                                    

P₁ . . . The region of the memory to be processed is determined by thefile address m_(A) and the digit address n_(C).

P₂ . . . The contents of the memory as specified above are unloaded intoACC and the memory file address is set at m_(C) prior to the nexttransmission step P₄.

P₃ . . . The digit address of the memory, the destination for thetransmission process, is specified as m_(C). The destinated region ofthe memory is specified via the steps P₂ and P₃.

P₄ . . . The contents of ACC are exchanged with the contents of theregions of the memory specified bu P₂ and P₃. The operand of X has noconnection with the present process.

    ______________________________________                                        (Type 3)                                                                      ______________________________________                                         ##STR13##                                                                    ______________________________________                                    

P₁ . . . The region of the memory to be processed is identified by thefile address m_(A) and the digit address n_(C).

P₂ . . . The contents of the memory region specified during P₁ areunloaded into ACC.

P₃ . . . The contents of the memory transmitted from ACC are sent to theregister X, completing the type 3 processing.

(IV) PROCEDURE OF EXCHANGING CONTENTS BETWEEN A SPECIFIC REGION OF THEMEMORY AND A DIFFERENT REGION (X→Y)

    ______________________________________                                        (Type 1)                                                                      ______________________________________                                         ##STR14##                                                                    ______________________________________                                    

P₁ . . . The first memory file address to be processed is specified asm_(A) and the first digit address as n_(E).

P₂ . . . The specific digit contents of the first memory are loaded intoACC and the second memory file address is specified as m_(B) forpreparation of the next step.

P₃ . . . The specific digit contents of the first memory containedwithin ACC are exchanged with the same digit contents of the secondmemory specified by P₂. The file address of the first memory isspecified as m_(A) in order to load the contents of the memory now inACC into the first memory.

P₄ . . . The contents of the second memory now in ACC are exchanged withthe contents of the first memory at the corresponding digit positions sothat the contents of the second memory are transferred to the firstmemory. Exchanges are carried out during the steps P₂ -P₄. The firstmemory is specified on by the file address m_(A), while the digitaddress is incremented to select a next address. Exchange is carried outprogressively digit by digit. The final digit value n_(A) is previouslyset at n₁ such that B_(L) =n₁ after the exchange operation between thefirst memory and the second has been effected throughout the all digitpositions, thus skipping the next step P₅ and completing the processingof Type 1.

P₅ . . . The program address P₂ is selected and the instructions for P₂to P₄ are executed repeatedly until B_(L) =n₁. The exchange operation isadvanced digit by digit.

    ______________________________________                                        (Type 2)                                                                      ______________________________________                                         ##STR15##                                                                    ______________________________________                                    

P₁ . . . The file address of the first memory to be processed isspecified as m_(A) and the digit address as n_(C).

P₂ . . . The contents of the specific digit position of the first memoryare unloaded into ACC and the file address of the second memory isspecified as m_(C) and ready to exchange.

P₃ . . . The digit address of the second memory, the destination for theexchange process, is specified as n_(O) to determine the destinatedmemory address.

P₄ . . . The contents of the first memory now within ACC are exchangedwith that of the second memory. At the same time the file address m_(B)of the first memory is again specified to transfer the contents of thefirst memory to the first memory.

P₅ . . . The digit address n_(C) of the first memory is specified todetermine the destination address of the first memory.

P₆ . . . The contents of the second memory now within ACC are exchangedwith the contents of the first memory.

    ______________________________________                                        (Type 3)                                                                      ______________________________________                                         ##STR16##                                                                    ______________________________________                                    

P₁ . . . The file address m_(A) of the first memory to be processed isspecified and the digit address n_(C) is specified.

P₂ . . . The contents of the first memory are loaded into ACC and thefile address m_(C) of the second memory is selected.

P₃ . . . The exchange is carried out between the first and second memoryso that the contents of the first memory are loaded into the secondmemory. Prior to the step P₄ the file address m_(B) of the first memoryis selected again.

P₄ . . . The exchange is effected between the contents of the secondmemory and the first memory.

    ______________________________________                                        (Type 4)                                                                      ______________________________________                                         ##STR17##                                                                    ______________________________________                                    

P₁ . . . The region of the memory to be processed is specified by thefile address m_(A) and the digit address n_(C).

P₂ . . . The contents of the memory region specified in P₁ above areloaded into ACC. The file address m_(B) is kept being selected prior tothe exchange with the contents of the register X.

P₃ . . . The exchange is effected between ACC and the register X so thatthe contents of the memory are shifted to the register X.

P₄ . . . Through the exchange between ACC containing the contents of theregister X and the memory, the contents of the register X aresubstantially transferred into the memory, thus accomplishing the Type 4processing.

(V) PROCEDURE OF EFFECTING A BINARY ADDITION OR SUBTRACTION OF A GIVENVALUE N ONTO A SPECIFIC REGION OF THE MEMORY

    ______________________________________                                         ##STR18##                                                                

    ______________________________________                                         ##STR19##                                                                    ______________________________________                                    

P₁ . . . The region of the memory to be processed is specified by thefile address m_(B) and the digit address n_(C).

P₂ . . . The contents of the memory specified by the step P₁ areunloaded into ACC. The memory file address is set again at m_(B) tospecify the same memory.

P₃ . . . The operand specifies the value N to be added and the contentsof the memory contained within ACC are added with the value N, theresults being loaded back to ACC.

P₄ . . . The sum contained with ACC is exchanged with the contents ofthe memory specified by the step P₂, thus completing the Type 1processing.

    ______________________________________                                         ##STR20##                                                                

    ______________________________________                                         ##STR21##                                                                    ______________________________________                                    

P₁ . . . The exchange is effected between the register X and ACC.

P₂ . . . The operand specifies the value N to be added and an additionis carried out on the contents of the register X now within ACC and thevalue N, with the results back to ACC.

P₃ . . . Through the exchange between the resulting sum within ACC andthe contents of the register X, the processing of Type 2 (X+N→X) isperformed.

    ______________________________________                                         ##STR22##                                                                

    ______________________________________                                         ##STR23##                                                                    ______________________________________                                    

P₁ . . . The region of the first memory to be processed is decided bythe file address m_(B) and the digit address n_(C).

P₂ . . . The contents of the memory specified by P₁ are loaded into ACC.The file address m_(C) of the second memory is specified to returnaddition results to the second memory.

P₃ . . . The operand specifies the value N to be added and the value Nis added to the contents of the memory now within ACC, with the resultsbeing loaded into ACC.

P₄ . . . The resulting sum within ACC is exchanged with the contents ofthe second memory as specified by P₂, thus completing the processing ofType 3.

    ______________________________________                                         ##STR24##                                                                

    ______________________________________                                         ##STR25##                                                                    ______________________________________                                    

P₁ . . . There are specified the file address m_(B) and the digitaddress n_(C) of the memory to be processed.

P₂ . . . Subtraction is carried out in such a way that the complement ofa subtrahend is added to a minuend and the F/F C remains set because ofthe absence of a borrow from a lower digit position.

P₃ . . . ACC is loaded with the subtrahend N.

P₄ . . . The complement of the subtrahend to "15" is evaluated andloaded into ACC.

P₅ . . . In the event that any borrow occurs during the subtraction, thecomplement of the subtrahend to "16" is added to the minuend. If aborrow free state is denoted as C=1, then a straight binary subtractionof ACC+C+M→ACC is effected.

P₆ . . . The resulting difference during P₅ is returned to the samememory through the exchange between ACC and that memory.

    ______________________________________                                         ##STR26##                                                                

    ______________________________________                                         ##STR27##                                                                    ______________________________________                                    

P₆ . . . To load the resulting difference during P₅ into the secondmemory, the file address m_(C) and the digit address n_(C) of the secondmemory are selected.

P₇ . . . Through exchange the resulting difference is transferred fromACC into the second memory as specified by the step P₆.

    ______________________________________                                        (Type 6)                                                                      ______________________________________                                         ##STR28##                                                                    ______________________________________                                    

P₁ . . . The file address m_(B) and the digit address n_(C) of thememory ready for the step P₅ are selected.

P₂ . . . Subtraction is carried out in the manner of adding thecomplement of a subtrahend to a minuend and the F/F C remains setbecause of the absence of a borrow from a lower digit position.

P₃ . . . ACC is loaded with the subtrahend N.

P₄ . . . The complement of the subtrahend to "15" is evaluated andloaded into ACC.

P₅ . . . To accomplish calculations with the contents of the register X,the memory as specified by P₁ is loaded with the contents of ACC.

P₆ . . . The contents of the register X are transmitted into ACC throughthe exchange process. After this step the memory contains the complementof the subtrahend to "15" and ACC contains the contents of X.

P₇ . . . ACC+M+C corresponds to X-N and the results of a binarysubtraction are loaded into ACC.

P₈ . . . The contents of ACC are exchanged with the contents of X andthe value of X-N is transmitted into X, thereby completing theprocessing of Type 6.

    ______________________________________                                         ##STR29##                                                                

    ______________________________________                                         ##STR30##                                                                    ______________________________________                                    

P₁ . . . The file address m_(B) and the digit address n_(C) of thememory to be processed are selected.

P₂ . . . One-digit subtraction is effected in the manner of adding thecomplement of a subtrahend to a minuend, in which case F/F C remainsset.

P₃ . . . ACC is loaded with a minuend.

P₄ . . . The exchange is effected between the memory (the subtrahend)and ACC and the memory file address remains as m_(B) for preparation ofP₇.

P₅ . . . The complement of a subtrahend in ACC to "15" is evaluated andloaded into ACC.

P₆ . . . In the event that there is no borrow from a lower digitposition, the complement of a subtrahend to "16" is added to a minuend.If a borrowless state is denoted as C=1, then N-M is substantiallyexecuted by ACC+C+M, the resulting difference being loaded into ACC.

P₇ . . . Since the memory file address remains unchanged during P₄, thedifference is unloaded from ACC back to the memory, thus completing theprocessing of Type 7.

    ______________________________________                                         ##STR31##                                                                

    ______________________________________                                         ##STR32##                                                                    ______________________________________                                    

P₁ . . . The file address m_(B) and the digit address n_(C) of thememory to be processed are selected.

P₂ . . . The contents specified by the step P₁ and corresponding to asubtrahend are loaded into ACC. The file address m_(C) of the secondmemory is specified for preparation of a step P₅.

P₃ . . . The complement of the subtrahend to "15" is evaluated andloaded into ACC.

P₄ . . . The operand is made a minuend plug "1". This subtraction is onedigit long and accomplished by adding the complement of the subtrahendto the minuend. A conventional complementary addition is defined asACC+C+M as in the Type 7 processing in the absence of a borrow asdefined by C=1. Since the ADI instruction carries C, ACC+1 is processedin advance. This completes the processing of Type 8 of N-M, the resultsbeing stored within ACC.

P₅ . . . The difference obtained from the step P₄ is transmitted intothe second memory specified by P₂.

    ______________________________________                                         ##STR33##                                                                

    ______________________________________                                         ##STR34##                                                                    ______________________________________                                    

P₁ . . . (When M+1) ACC is loaded with a binary number "0001" (=1).

P_(1') . . . (When M-1) ACC is loaded with a binary number "1111" (=15).

P₂ . . . The file address m_(B) and the digit address n_(C) of thememory to be processed are selected.

P₃ . . . The contents of the memory specified by P₂ are added to thecontents contained within ACC during P₁ or P₁ ', the sum thereof beingloaded into ACC. In the case of P₁ ACC+1 and in the case of P₁ ' ACC-1.

P₄ . . . The results are unloaded from ACC to the original memoryposition, thus completing the processing fashion of Type 9.

(VI) PROCEDURE OF EFFECTING A DECIMAL ADDITION OR SUBTRACTION BETWEEN ASPECIFIC REGION OF THE MEMORY AND A DIFFERENT REGION

    ______________________________________                                         ##STR35##                                                                

    ______________________________________                                         ##STR36##                                                                    ______________________________________                                    

P₁ . . . The first digit position of the first memory to be processed isidentified by the file address m_(A) and the digit address n_(E).

P₂ . . . The carry F/F C is reset because of a carry from a lower digitposition in effecting a first digit addition.

P₃ . . . The contents of the specific digit position of the first memoryare loaded into ACC and the file address m_(B) of the second memory isselected in advance of additions with the contents of the second memoryduring P₄.

P₄ . . . "6" is added to the contents of the specific digit position ofthe first memory now loaded into ACC for the next succeeding step P₅wherein a decimal carry is sensed during addition.

P₅ . . . ACC already receives the contents of the first memorycompensated with "6" and a straight binary addition is effected upon thecontents of ACC and the contents of the second memory at thecorresponding digit positions, the results being loaded back to ACC. Inthe event a carry is developed during the binary addition at the fourthbit position, P₇ is reached without passing P₆. The presence of thecarry during the fourth bit addition implies the development of adecimal carry.

P₆ . . . In the event the decimal carry failed to develop during theaddition P₅, "6" for the process P₄ is overruded. An addition of "10" issame as a subtraction of "6".

P₇ . . . The one-digit decimal sum is unloaded from ACC into the secondmemory and the digit address is incremented for a next digit additionand the file address m_(A) of the first memory is selected. The finaldigit to be added is previously set at n₁. Since BL=n₁ after the overalldigit addition is effected upon the first and second memory, the nextsucceeding step P₈ is skipped to thereby complete the processing of Type1.

P₈ . . . The program address P₃ is selected and the instructions P₃ -P₇are repeatedly executed until BL=n₁. A decimal addition is effecteddigit by digit.

    ______________________________________                                         ##STR37##                                                                

    ______________________________________                                         ##STR38##                                                                    ______________________________________                                    

P₁ . . . The first digit position of the first memory to be processed isspecified by the file address m_(A) and the digit address n_(E).

P₂ . . . Subtraction is performed in the manner of adding the complementof a subtrahend to a minuend and F/F C is set because of the absence ofa borrow from a lower digit position during the first digit subtraction.

P₃ . . . The contents of the specific digits in the first memory, thesubtrahend, are loaded into ACC and the file address m_(B) of the secondmemory is specified in advance of the step P₇ with the second memory.

P₄ . . . The complement of the subtrahend to "15" is evaluated andloaded into ACC.

P₅ . . . In the event that there is no borrow from a lower digit place,the complement of the subtrahend is added to the minuend to perform asubtraction. On the contrary, in the presence of a borrow, thecomplement of the subtrahend is added to the minuend. If a borrowlessstate is denoted as C=1, then a binary addition of ACC+C+M→ACC iseffected. The development of a carry, as a consequence of the executionof the ADSCK instruction, implies failure to give rise to a borrow andleads to the step P₇ without the intervention of the step P₆. Underthese circumstances the addition is executed with the second memory,thus executing substantially subtraction between the first and secondmemories.

P₆ . . . In the case where no carry is developed during the execution ofthe ADCSK instruction by the step P₅, the calculation results are of thesexadecimal notation and thus converted into a decimal code bysubtraction of "6" (equal to addition of "10").

P₇ . . . The resulting difference between the first and second memoriesis transmitted from ACC into the second memory. The digit address isincremented and the file address m_(A) of the first memory is specifiedin advance of a next succeeding digit subtraction. The final digit to besubtracted is previously determined as n₁. Since BL=n₁ after theoverall-digit subtraction has been completed, the next step P₈ isskipped to thereby conclude the processing of Type 2.

P₈ . . . After selection of the program address P₃ the instructions P₃-P₇ are repeatedly executed until BL=n₁. The decimal subtraction isadvanced digit by digit.

(VII) PROCEDURE OF SHIFTING ONE DIGIT THE CONTENTS OF A SPECIFIC REGIONOF THE MEMORY

    ______________________________________                                        (Type 1) Right Shift                                                          ______________________________________                                         ##STR39##                                                                    ______________________________________                                    

P₁ . . . The file address m_(A) and the digit address n_(A) of thememory to be processed are determined.

P₂ . . . ACC is loaded with "0" and ready to introduce "0" into the mostsignificant digit position when the right shift operation is effected.

P₃ . . . The exchange is carried out between XCC and the memory and thedigit address is decremented to specific a one digit lower position. Thememory address is still at m_(A). XD is repeated executed through P₄ andP₃. By the step ACC←→M "0" is transmitted from ACC to the mostsignificant digit position of the memory which in turn provides itsoriginal contents for ACC. When the digit address is down via B and XDis about to be executed at P₃ via P₄, the second most significant digitis selected to contain the original content of the most significantdigit position which has previously been contained within ACC. At thistime ACC is allowed to contain the contents of the second mostsignificant digit position. The least significant digit is previouslyselected as n₂. If the transmission step reaches the least significantdigit position BL=n₂ is satisfied and P₄ is skipped. In other words, thedigit contents are shifted down to thereby conclude the processing ofType 1.

P₄ . . . XD is repeated at P₃ until BL=V.

    ______________________________________                                        (Type 2) Left Shift                                                           ______________________________________                                         ##STR40##                                                                    ______________________________________                                    

P₁ . . . The file address m_(A) and the least significant digit n_(E) ofthe memory to be processed are determined.

P₂ . . . ACC is loaded with "0" and ready to introduce "0" into theleast significant digit position when the left shift operation isstarted.

P₃ . . . The exchange is carried out between ACC and the memory and thedigit address is incremented to specify a one digit upper position. Thememory address is still at m_(A). XD is repeated executed through P₄ andP₃. By the step ACC→M, "0" is transmitted from ACC to the leastsignificant digit position of the memory which in turn provides itsoriginal contents for ACC. When the digit address is up via P₃ and XD isabout to be executed at P₃ via P₄, the second least significant digit isselected to contain the original content of the least significant digitposition which has previously been contained within ACC. At this timeACC is allowed to contain the contents of the second least significantdigit position. The most significant digit is previously selected as n₁.If the transmission step reaches the most significant digit position,BL=n₁ is satisfied and P₄ is skipped. In other words, the digit contentsare shifted up to thereby conclude the processing of Type 2.

P₄ . . . XI is repeated at P₃ until BL=V.

(VIII) PROCEDURE OF SETTING OR RESETTING A ONE-BIT CONDITION F/FASSOCIATED WITH A SPECIFIC REGION OF THE MEMORY

    ______________________________________                                        (Type 1)                                                                      ______________________________________                                         ##STR41##                                                                    ______________________________________                                    

P₁ . . . The file address m_(B) and the digit address n_(C) of a regionof the memory to be processed are determined.

P₂ . . . "1" is loaded into a desired bit N within the digit position ofthe memory specified by P₁, thus concluding the processing of Type 1.

    ______________________________________                                        (Type 2)                                                                      ______________________________________                                         ##STR42##                                                                    ______________________________________                                    

P₁ . . . The file address m_(B) and the digit address n_(C) of a regionof the memory to be processed are determined.

P₂ . . . "0" is loaded into a desired bit N within the digit position ofthe memory specified by P₁, thus concluding the processing of Type 2.

(IX) PROCEDURE OF SENSING THE STATE OF THE ONE-BIT CONDITIONAL F/FASSOCIATED WITH A SPECIFIC REGION OF THE MEMORY AND CHANGING A NEXTPROGRAM ADDRESS (STEP) AS A RESULT OF THE SENSING OPERATION

    ______________________________________                                         ##STR43##                                                                

    ______________________________________                                    

P₁ . . . There are specified the file address m_(B) and the digitaddress n_(C) where a desired one-bit conditional F/F is present.

P₂ . . . In the case where the contents of the bit position(corresponding to the conditional F/F) specified by N within the memoryregion as selected during P₁ assume "1", the step proceeds to P₄ withskipping P₃, thus executing the operation OP₁. In the event that thedesired bit position bears "0", the next step P₃ is skipped.

P₃ . . . When the foregoing P₂ has been concluded as the conditional F/Fin the "0" state, the program step P_(n) is selected in order to executethe operation OP₂.

(X) PROCEDURE OF DECIDING WHETHER THE DIGIT CONTENTS OF A SPECIFICREGION OF THEMEMORY REACH A PRESELECTED NUMERAL AND ALTERING A NEXTPROGRAM ADDRESS (STEP) ACCORDING TO THE RESULTS OF THE DECISION

    ______________________________________                                         ##STR44##                                                                

    ______________________________________                                    

P₁ . . . The region of the memory which contains contents to be decidedis identified by the file address m_(B) and the digit address n_(C).

P₂ . . . The contents of the memory as identified during P₁ are unloadedinto ACC.

P₃ . . . The contents of ACC are compared with the preselected value Nand if there is agreement the step advances toward P₅ without executingP₄ to perform the operation OP₁. P₄ is however reached if the contentsof ACC are not equal to N.

P₄ . . . The program address (step) P_(n) is then selected to performthe operation OP₂.

(XI) PROCEDURE OF DECIDING WHETHER THE PLURAL DIGIT CONTENTS OF ASPECIFIC REGION OF THE MEMORY ARE EQUAL TO A PRESELECTED NUMERAL ANDALTERING A PROGRAM STEP ACCORDING TO THE RESULTS OF THE DECISION

    ______________________________________                                         ##STR45##                                                                

    ______________________________________                                    

P₁ . . . The region of the memory to be judged is identified by the fileaddress m_(B) and the first digit address n_(E).

P₂ . . . The value N is loaded into ACC for comparison.

P₃ . . . The value V within ACC is compared with the digit contents ofthe specific region of the memory and if there is agreement P₅ isreached without passing P₄ to advance the comparison operation towardthe next succeeding digit. P₄ is selected in a non-agreement.

P₄ . . . In the case of a non-agreement during P₃ the program address(step) P_(n) is specified to execute the operation forthwith.

P₅ . . . The digit address is incremented by adding "1" thereto. Thisstep is aimed at evaluating in sequence a plurality of digits within thememory. The ultimate digit to be evaluated is previously determined as(V). The comparison is repeated throughout the desired digit positions.If a non-agreement state occurs on the way, the operation OP₂ isaccomplished through P₄. In the case where the agreement state goes ontill BL=V, there is selected P₇ rather than P₆ to perform the operationOP₁.

P₆ . . . When the agreement state goes on during P₅, P₃ is reverted forevaluation.

(XII) PROCEDURE OF DECIDING WHETHER THE CONTENTS OF A SPECIFIC REGION OFTHE MEMORY ARE SMALLER THAN A GIVEN VALUE AND DECIDING WHICH ADDRESS(STEP) IS TO BE EXECUTED

    ______________________________________                                         ##STR46##                                                                

    ______________________________________                                    

P₁ . . . The file address m_(B) and the digit address n_(C) of thememory are decided.

P₂ . . . The contents of the memory as specified during P₁ are unloadedinto ACC.

P₃ . . . N is the value to be compared with the contents of the memoryand the operand area specifies 16-N which in turn is added to thecontents of ACC, the sum thereof being loaded back to ACC. Theoccurrence of a fourth bit carry during the addition suggests that theresult of the binary addition exceeds 16, that is, M+(16-N)≧16 and henceM≧N. The step is progressed toward P₄.

P₄ . . . When M≧N is denied, the program step P_(n) is selected to carryout the operation OP₂.

(XIII) PROCEDURE OF DECIDING WHETHER THE CONTENTS OF A SPECIFIC REGIONOF THE MEMORY ARE GREATER THAN A GIVEN VALUE AND DECIDING WHICH ADDRESS(STEP) IS TO BE EXECUTED

    ______________________________________                                         ##STR47##                                                                

    ______________________________________                                    

P₁ . . . The file address m_(B) and the digit address n_(C) of thememory are decided.

P₂ . . . The contents of the memory as specified during P₁ are unloadedinto ACC.

P₃ . . . N is the value to be compared with the contents of thememoryand the operand area specifies 15-N which in turn is added to thecontents of ACC, the sum thereof being loaded back to ACC. Theoccurrence of a fourth bit carry during the addition suggests that theresults of binary addition exceeds 16, that is, M+(15-N)≧16 and henceM≧N+1 and M>N. The step is progressed toward P₅ with skipping P₄, thusperforming the operation OP₁. In the absence of a carry (namely, M>N)the step P₄ is reached.

P₄ . . . When M≧N is denied, the program address (Step) P_(n) isselected to carry out the operation OP₂.

(XIV) PROCEDURE OF DISPLAYING THE CONTENTS OF A SPECIFIC REGION OF THEMEMORY

    ______________________________________                                        (Type 1)                                                                      ______________________________________                                         ##STR48##                                                                    ______________________________________                                    

P₁ . . . The bit number n₁ of the buffer register W is loaded into ACCto reset the overall contents of the buffer register W for generatingdigit selection signals effective to drive a display panel on a timesharing basis.

P₂ . . . After the overall contents of the register W are one bitshifted to the right, its first bit is loaded with "0". This procedureis repeated via P₄ until C₄ =1 during P₃, thus resetting the overallcontents of W.

P₃ . . . The operand I_(A) is decided as "1111" and AC+1111 is effected(this substantially corresponds to ACC-1). Since ACC is loaded with n₁during P₁, this process is repeated n₁ times. When the addition of"1111" is effected following ACC=0, the fourth bit carry C₄ assumes "0".When this occurs, the step is advanced to P₄. Otherwise the step isskipped up to P₅.

P₄ . . . When the fourth bit carry C₄ =0 during ACC+1111, the overallcontents of W are reduced to "0" to thereby complete all the pre-displayprocesses. The first address P₆ is set for the memory display steps.

P₅ . . . In the event that the fourth bit carry C₄ =1 during ACC+1111,the overall contents of W have not yet reduced to "0". Under thesecircumstances P₂ is reverted to repeat the introduction of "0" into W.

P₆ . . . The first digit position of the memory region which containsdata to be displayed is identified by the file address m_(A) and thedigit address n_(A).

P₇ . . . After the contents of the register W for generating the digitselection signals are one bit shifted to the right, its first bitposition is loaded with "1" and thus ready to supply the digit selectionsignal to the first digit position of the display.

P₈ . . . The contents of the specific region of the memory are unloadedinto ACC. The file address of the memory still remains at m_(A), whereasthe digit address is decremented for the next succeeding digitprocessing.

P₉ . . . The contents of the memory is shifted from ACC to the bufferregister F. The contents of the register F are supplied to the segmentdecoder SD to generate segment display signals.

P₁₀ . . . To lead out the contents of the register W as display signals,the conditional F/F N_(p) is supplied with "1" and placed into the setstate. As a result of this, the contents of the memory processed duringP₉ are displayed on the first digit position of the display.

P₁₁ . . . A count initial value n₂ is loaded into ACC to determine a onedigit long display period of time.

P₁₂ . . . ACC-1 is carried out like P₃. When ACC does not assume "0"(when C₄ =1) the step is skipped up to P₁₄.

P₁₃ . . . A desired period of display is determined by counting thecontents of ACC during P₁₂. After the completion of the counting P₁₅ isreached from P₁₃. The counting period is equal in length to a one-digitdisplay period of time.

P₁₄ . . . Before the passage of the desired period of display the stepis progressed from P₁₂ to P₁₄ with skipping P₁₃ and jumped back to P₁₂.This procedure is repeated.

P₁₅ . . . N_(p) is reset to stop supplying the digit selection signalsto the display. Until N_(p) is set again during P₁₀, overlapping displayproblems are avoided by using the adjacent digit signals.

P₁₆ . . . The register W is one bit shifted to the right and its firstbit position is loaded with "0". "1" introduced during P₇ is one bitshifted down for preparation of the next succeeding digit selection.

P₁₇ . . . It is decided whether the ultimate digit of the memory to bedisplayed has been processed and actually whether the value n_(E) of thelast second digit has been reached because the step P₈ of B_(L) -1 is ineffect.

P₁₈ . . . In the event that ultimate digit has not yet been reached, P₈is reverted for the next succeeding digit display processing.

P₁₉ . . . For example, provided that the completion of the displayoperation is conditional by the flag F/F FA, FA=1 allows P₂₀ to beskipped, thereby concluding all the displaying steps.

P₂₀ . . . If FA=1 at P₁₉, the display steps are reopened from the firstdisplay and the step is jumped up to P₆.

    ______________________________________                                        (Type 2)                                                                      ______________________________________                                         ##STR49##                                                                    ______________________________________                                    

P₁ . . . The bit number n₁ of the buffer register W is loaded into ACCto reset the overall contents of the buffer register W for generatingdigit selection signals effective to drive a display panel on a timesharing basis.

P₂ . . . After the overall contents of the register W are one bitshifted to the right, its first bit is loaded with "0". This procedureis repeated via P₄ until C₄ =1 during P₃, thus resetting the overallcontents of W.

P₃ . . . The operand I_(A) is decided as "1111" and AC+1111 is effected(this substantially corresponds to ACC-1). Since ACC is loaded with n₁during P₁, this process is repeated n₁ times. When the addition of"1111" is effected following ACC=0, the fourth bit carry C₄ assumes "0".When this occurs, the step is advanced to P₄. Otherwise the step isskipped up to P₅.

P₄ . . . When the fourth bit carry C₄ =0 during ACC+1111, the overallcontents of W are reduced to "0" to thereby complete all the pre-displayprocesses. The first address P₆ is set for the memory display steps.

P₅ . . . In the event that the fourth bit carry C₄ =1 during ACC+1111,the overall contents of W have not yet reduced to "0". Under thesecircumstances P₂ is reverted to repeat the introduction of "0" into W.

P₆ . . . The upper four bits of the first digit position of the memoryregion which contains data to be displayed are identified by the fileaddress m_(A) and the digit address m_(A).

P₇ . . . The contents of the specific region of the memory are unloadedinto ACC. The file address of the memory still remains at m_(A), whereasthe digit address is decremented to specify the lower four bits.

P₈ . . . The contents of ACC, the upper four bits, are transmitted intothe temporary register X.

P₉ . . . The contents of the specific region of the memory are unloadedinto ACC. The file address of the memory still remains at m_(A), whereasthe digit address is decremented to specify the upper four bits of thenext succeeding digit.

P₁₀ . . . The contents of ACC are unloaded into the stack register SAand the contents of the temporary register X into the stack register SX.

P₁₁ . . . After the contents of the register W for generating the digitselection signals are one bit shifted to the right, its first bitposition is loaded with "1" and thus ready to supply the digit selectionsignal to the first digit position of the display.

P₁₂ . . . To lead out the contents of the register W as display signals,the conditional F/F N_(p) is supplied with "1" and placed into the setstate. As a result of this, the contents of the memory processed duringP₁₀ are displayed on the first digit position of the display.

P₁₃ . . . A count initial value n₂ is loaded into ACC to determine a onedigit long display period of time.

P₁₄ . . . ACC-1 is carried out like P₃. When ACC assumes "0" P₁₅ isreached and when ACC≠0 (when C₄ =1) the step is skipped up to P₁₆. Thisprocedure is repeated.

P₁₅ . . . A desired period of display is determined by counting thecontents of ACC during P₁₄. After the completion of the counting P₁₇ isreached from P₁₅. The counting period is equal in length to a one-digitdisplay period of time.

P₁₆ . . . Before the passage of the desired period of display the stepis progressed from P₁₄ to P₁₆ with skipping P₁₅ and jumped back to P₁₄.This procedure is repeated.

P₁₇ . . . N_(p) is reset to stop supplying the digit selection signalsto the display. Until N_(p) is set again during P₁₀, overlapping displayproblems are avoided by using the adjacent digit signals.

P₁₈ . . . The register W is one bit shifted to the right and its firstbit position is loaded with "0". "1" introduced during P₇ is one bitshifted down for preparation of the next succeeding digit selection.

P₁₉ . . . It is decided whether the ultimate digit of the memory to bedisplayed has been processed and actually whether the value n_(E) of thelast second digit has been reached because the step p₉ of B_(L) -1 is ineffect.

P₂₀ . . . In the event that ultimate digit has not yet been reached, P₇is reverted for the next succeeding digit display processing.

    ______________________________________                                        (XV) PROCEDURE OF DECIDING WHICH KEY SWITCH                                   IS ACTUATED (SENSING ACTUATION OF ANY KEY                                     DURING DISPLAY                                                                ______________________________________                                         ##STR50##                                                                                    ##STR51##                                                     ______________________________________                                    

P₁ -P₁₈ . . . The display processes as discussed in (XIV) above.

P₁₉ . . . After the overall digit contents of the register W aredisplayed, the flag F/F FC is set to hold all the key signals I_(l)-I_(n) at a "1" level.

P₂₀ . . . The step is jumped to P₃₀ as long as any one of the keysconnected to the key input KN₁ is actuated.

P₂₂ -P₂₇ . . . It is decided whether any one of the keys each connectedto the respective key inputs KN₂ -KF₂ and in the absence of anyactuation the step is advanced toward the next succeeding step. To thecontrary, the presence of the key actuation leads to P₃₀.

P₂₈ . . . When any key is not actuated, F/F FC is reset to therebycomplete the decision as to the key actuations.

P₂₉ . . . The step is jumped up to P₆ to reopen the display routine.

P₃₀ . . . When any key is actually actuated, the memory digit address isset at n₁ to generate the first key strobe signal I₁.

P₃₁ . . . It is decided if the first key strobe signal I₁ is applied tothe key input KN₁ and if not the step is advanced toward P₃₃.

P₃₂ . . . When the first key strobe signal I₁ is applied to the keyinput KN₁, which kind of the keys is actuated is decided. Thereafter,the step is jumped to P_(A) to provide proper controls according to thekey decision. After the completion of the key decision the step isreturned directly to P₁ to commence the displaying operation again(P_(Z) is to jump the step to P₁)

P₃₃ -P₃₈ . . . It is sequentially decided whether the keys coupled withthe first key strobe signal I₁ are actuated. If a specific key isactuated, the step jumps to P_(B) -P_(D) for providing appropriatecontrols for that keys.

P₃₉ . . . This step is executed when no key coupled with the first keystrobe signal I₁. This step is to increment the digit address of thememory for the developments of the key strobe signals.

P₄₁ and up . . . The appropriate key strobe signals are developed andKN₁ -KF₂ are sequentially monitored to decide what kind of the keys areactuated. Desired steps are then selected to effects control steps forthose actuated keys.

P_(A) and up . . . Control steps for the first actuated keys.

P_(X) . . . P₁ is returned to reopen the display operation after thecontrol steps for the first key.

The foregoing is the description of the respective major processingevents in the CPU architecture.

By reference to FIGS. 6 and 7 an example of the display operation of acalculator implementing the display device according to the presentinvention will now be described in detail.

FIG. 7 exemplifies a manner by which a pattern "I" is displayed on upperand lower rows of the 7×5 dot matrix display panel by use of the segmentsignals S₁ -S₄₀ and the opposing electrode output signals H₁ -H₇ afterthe storage contains "11F1144744" (see FIG. 7(b)). The displaying datastorage area DRM stores temporarily those displaying data as depicted inFIG. 8. The encoded information is stored within the areas (1)-(16),with the area (1) storing the encoded information "11F1144744." Also,the same encoded information is stored in part of the RAM of the CPU asshown in FIG. 9 as do the areas (1)-(16).

The displaying data storage area DRM of FIG. 8 is able to store thecharacter data (1)-(16) but actually the encoded information within thearea covering from B_(B) B_(L) (0, 0) to B_(M) B_(L) (5, 7) may bedisplayed and all of the character data are not displayed at a time. Thecharacters on the display panel shifts dot by dot at a given period oftime by shifting the selected address B_(M) B_(L) (0, 0)-B_(M) B_(L) (B,F) of the displaying data storage area DRM in the display controlcircuitry DSC digit by digit at the given period of time through theaction of the CPU.

FIG. 10 is a flow chart of the running display operation which achievesdot by dot movement of the display contents. By the step N₁ the displayis disabled and the DRM is loaded with the data to be running displayed.The step N₂ loads the count indicative of the speed of the runningdisplay operation into the display counter. The step N₃ loads the nextaddress of the DRM into the accumulator to shift the address digit bydigit. The step N₄ enables the display operation and the step N₅decrements the display counter. The display operation goes on until thecounter reaches "zero" as sensed by the counter which determines thespeed of the running display operation. The step N₇ disables the displayoperation, followed by the SHIFT routine. The running display mode iscompleted in this manner.

FIG. 11 is a flow chart for explanation of the operation shown in FIG.10 through the utilization of the circuit arrangement of FIGS. 2 through4. Assume now that the displaying data have already stored within theRAM of the CPU. It is noted that the respective steps n₁, n₂ . . . n₁₁₁are listed in FIG. 12. Each of the characters 0, 1, 2, . . . 8, 9, a, b,c, . . . x, y, z is stored within the RAM of the CPU in the form of theencoded signals of FIG. 13. As is clear from FIG. 13, if the lower 4bits are "0000", then the numerical information is present. If the lower4 bits are "0001", the alphabetic characters a-p are evaluated and ifthe lower 4 bits are "0010" the remaining alphabetic characters q-z areevaluated.

The steps and their contents in FIG. 11 will now be discussed.

n₁ : the address EO of the RAM of the CPU is selected.

n₂ : it is decided as to whether the address EO is "0000"

n₃ : it is decided as to whether the address EO is "0001"

n₄ : it is decided as to whether the address EO is "0010"

n₅ : the selected bit C₁ of the RAM is set and C₂ and C₃ are reset.

n₆ : the selected bit C₂ of the RAM is set and C₁ and C₃ are reset.

n₇ : the selected bit C₃ of the RAM is set and C₁ and C₂ are reset.

n₈ : the address E₁ of the RAM of the CPU is selected.

n₉ : whether the address E₁ is "0000" is decided.

n₁₀ : whether the address E₁ is "0001" is decided.

n₁₁ : whether the address E₁ is "1111" is decided.

n₁₂ : whether C₁ is set or reset is decided.

n₁₃ : whether C₂ is set or reset is decided.

n₁₄ : the character pattern corresponding to the data "0" is loaded intothe displaying data storage area DRM (the program effective indisplaying the character "I" is illustrated in FIG. 14).

n₁₅ : the character pattern indicative of the data "A" is loaded intothe displaying data storage area DRM.

n₁₆ : the character pattern indicative of the data "Q" is loaded intothe storage area.

n₁₇ -n₂₆ : the steps n₁₂ -n₁₆ are repeated.

n₂₇ : the address E₂ of the RAM of the CPU is selected.

n₂₈ -n₃₃ : same as the above mentioned steps n₂ -n₇.

n₃₄ : the address E₃ of the RAM of the CPU is selected.

n₃₅ up to n₅₂ : same as the above steps n₁₂ -n₂₆.

n₅₃ : the address FF of the RAM of the CPU is selected.

n₅₄ up to n₇₁ : same as the steps n₁₂ -n₂₆.

n₇₂ : the value m is loaded into the counter CO which may be part of theRAM.

n₇₃ : the address BF of the DRM is selected.

n₇₄ : the file address B is shifted by one digit via the subroutine SR.This step is shown in FIG. 15.

S₁ TML: upon the completion of the subroutine the address of the ROM isstored to return to the main routine.

S₂ EXO: exchange takes place between the memory storing the selectedaddress of the RAM of the CPU and the accumulator ACC. The address ofthe memory file remains unchanged.

S₃ READ: the selected address of the DRM is read into the accumulator.

S₄ EXO: exchange takes place between the contents of the accumulator andthe contents of the memory stored at the selected address of the RAM ofthe CPU.

S₅ STOR: the contents of the accumulator ACC are unloaded into the DRMat the selected address.

S₆ EXO: exchange occurs between the contents of the accumulator ACC andthe contents of the RAM.

S₇ DECB: the digit address counter B_(L) is decremented. By thefollowing steps the contents of the DRM are shifted via repeatedexecution of the program with varying the digit address. Eventually,

S₁₆ RIT: the address of the ROM is regained for the main routine.

Thereafter, the respective file addresses 9, 7, 5, 3, 1 are shifted byone digit through the steps n₇₅ -n₈₄. The steps n₈₅ -n₉₀ makes up aroutine for transferring the contents of the address B_(M), B_(L) (1, 0)into the addresses B, F. In this manner, the lower 3 dots of FIG. 6 areshifted left by one dot. The steps n₉₁ -n₁₀₁ are a routine for shiftingleft the respective file addresses A, 8, 6, 4, 2, 0 by one dot in thesame manner as the steps n₇₃ -n₈₄.

The steps n₁₀₂ -n₁₀₇ shift the contents of the address B_(M) B_(L) : 0,0 to AF. Accordingly, the steps n₉₁ -n₁₀₇ shift left the upper 4 dots ofthe character by one dot. The step n₁₀₈ sets the display controllingflag N₁ so that the segment driver SED provides the segment signals S₁-S₄₀, thus displaying the data out of the displaying storage area DM. Bythe action of the step n₁₀₉ the counter keeps decrementing until CO="0."When CO="0" the instruction n₁₁₁ places the displaying controlling flagN₁ into the reset state. Consequently, SED turns OFF S₁ -S₄₀, thusdisabling the display operation. Then, the step n₇₂ is returned to shiftthe contents of the displaying data storage area during the disableperiod.

FIG. 16 is a flow chart associated with the display operation on keyedinputs, wherein a display of the actuated key is shifted each time thekeys are actuated as is obvious in the calculator art other thanshifting that dot by dot.

In FIG. 16, the step m₁ should be inserted into an appropriate positionin the routine shown FIG. 11, followed by the step m₂ when any keyedinput is sensed. The step m₂ is executed to check if a display key isactuated and, if NO, regards that a character key not the display keyhas been actuated, thus leading to the step m₃ by which the charactercode corresponding to that character key is introduced into the firstcharacter position of the register within the memory. The step m₄ placesthat character pattern into the displaying data storage area DRM. Thestep m₅ sets the displaying flag N₁ and enables the contents of the DRMto be displayed. When the second character is inputted, a sequence ofthe steps m₆ m₇ m₈ is executed to transfer that character code into thesecond character position of the register within the memory. The step m₉discontinues the display operation. The step m₁₀ shifts the 6 dotswithin the data storage area DRM. After the second character pattern isloaded into DRM, the instruction m₁₂ starts the display operation. Inthis manner, keyed information is loaded and displayed simultaneously.If the display key DK is actuated subsequently to the introduction ofthe character, then the routine 4 as shown in FIG. 11 is selected toattain the dot by dot movement on the display panel.

Whereas the present invention has been described with respect tospecific embodiments thereof, it will be understood that various changesand modifications will be suggested to one skilled in the art, and it isintended to encompass such changes and modifications as fall within thescope of the appended claims.

We claim:
 1. An electronic calculator and display system comprising:acentral processing unit; a dot matrix display arranged in a number ofdisplay segments; display information memory means for storinginformation to be displayed at fixed locations therein; display read andwrite control circuit for storing and reading information in saiddisplay information memory means; display buffer means for reading anddecoding the information stored in said display information memorymeans; display address decoder means responsive to said centralprocessing unit for selecting addresses within said display informationmemory from which information is read and decoded by said display buffermeans; segment driver means for converting the decoded informationdeveloped by said display buffer means into individual segment signalsfor application to the individual display segments of said dot matrixdisplay; information volume detection means for producing a displayshift signal when the number of characters of said information to bedisplayed stored in said display information memory means exceeds thenumber of display segments; said display address decoder means and saidcentral processing unit sequentially shifting the addresses of saiddisplay information memory means to be read by said display buffer meansin response to the production of said display shift signal by saidinformation volume detection means to thereby shift said informationacross said display to form a running display pattern.
 2. The system ofclaim 1 wherein said information volume detection means further includesnumerical information determination means inhibiting the production ofsaid display shift signal when said information to be displayed isnumerical information produced by an arithmetic operation.